Switch-Box and Connection-Box for Segmented Interconnection in Hierarchical FPGA
نویسندگان
چکیده
This paper presents a new switch-box (SB) and connection-box (CB) design combination for segmented interconnection, which is the bottom level interconnection in our hierarchical FPGA. SB & CB design candidates are first pre-screened by analysis based on maze routing algorithm. Then the structure with the best routability is chosen from candidates by benchmark experiment evaluation. The new structure results in 54% SB and CB area reduction and 14% chip area reduction when implemented in our hierarchical FPGA chip.
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